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rev.1.00 dec 01, 2004 page 1 of 46 rej03b0116-0100z description the 32186 group is a 32-bit single-chip risc microcom puter with built-in flash memory. to accomplish high- precision arithmetic operations, it incorporates a fully ieee754 compliant, single-precision fpu. this microcomputer contains a variety of peripheral functio ns. with the software necessary to run these peripheral functions stored in its large-capacity flash memory, this microcomputer meets the needs of application systems for high functionality, high-performance arithmetic capability , and sophisticated control, thereby adaptation to the embedded applications can be easily configured. table 1.0.1 product list note 1: this does not guarantee conti nuous operation and there is a limitation on the length of use (temperature profile). features ? cpu .............................. m32r-fpu core (m32r family common instructio n set + single-precision fpu / bit manipulation instructions) ? pipeline structure .......................................................................................................... ................... 6-stage structure ? instruction set ............................................... ..................................... 100 discrete instruction s / 6 addressing modes ? instruction format .......................................................................................................... ................... 6 bit/32-bit length ? built-in multiplier-accumulator (dsp function instructions) ? minimum instruction execution time .............. .............. .............. ............. 12.5ns (at f(cpuclk) = 80 mhz oper ation) ? built-in flash memory ? built-in ram ? virtual-flash emulation function ............................................................................................ ...... 8 kbytes x 8 blocks ? interrupt controller .............................................................................................. 41 interr upt sources, 8 priority levels ? wait controller ............ .............. .............. ... can be extended 0-15 wait cycles and external signal for each of 4 areas ? i/o port .......................................................................................................... 97 ports (selectable from 3 input levels) ? external interrupt input pin ................................................................................................ ............................... 27 pins ? dmac ........................................................................................................................ .............. ............ .... 10 channels ? multijunction timers (mj t) .................................................................................................. ...................... 55 channels ? a/d converter ................................................................................. 16 channels 10-bit converter (sample & hold x 2) ? serial interface .............. .............. 4 channels (clock synchronous/asynchronous), 2 channels (clock synchronous) ? can (can specification 2.0b active) ......................... ............................. 2 channels, each having 32 message slots ? direct ram interface (dri) ? real-time debugger (rtd) ? non-break debug (nbd) ? jtag (boundary scan function) ? debug interface common to the m32r family (sdi: scalable debug interface) ? package ..................................................................................................................... .... 144 pin lqfp (0.5mm pitch) applications automobile equipment control (e.g., engine, abs, at, ccd, and radar sensing applications), industrial equipment system control, and high-function oa equipment (e.g., ppc) since this group is under development, its specifications are subject to change. type name rom capacity ram capacity frequency power supply voltage temperature range (note 1) at single- supply at double- supplies M32186f8vfp 1 mbytes 64 kbytes 80mhz 5v or 3.3v 5v, 3.3v -40c to +125c rej03b0116-0100z rev.1.00 dec 01, 2004 32186 group 32-bit risc microcomputer
rev.1.00 dec 01, 2004 page 2 of 12 rej03b0116-0100z 32186 group 1.1 outline of the 32186 group 1.1 outline of the 32186 group 1.1.1 m32r family cpu core wi th built-in fpu (m32r-fpu) (1) based on a risc architecture ? the 32186 group (hereafter simply the 32186) is a 32-bit risc single-chip microcomputer. the m32r- fpu incorporates a fully ieee 754-compliant, single- precision fpu in order to materialize the common instruction set and the high-precisi on arithmetic operation of the m32r cpu. the 32186 products are built around the m32r-fpu and incorporates flash memo ry, ram and various peripheral functions, all integrated into a single chip. ? the m32r-fpu is constructed ba sed on a risc architecture. me mory is accessed using load/store instructions, and various arithmetic /logic operations are executed using register-to-register operation instructions. ? the m32r-fpu internally contains sixteen 32-bit gene ral-purpose registers. the in struction set consists of 100 discrete instructions in total (83 instructions common to the m32r family plus 17 fpu and extended instructions). these instructions are either 16 bits or 32 bits long. ? in addition to the ordinary load/store instructions , the m32r-fpu supports compound instructions such as load & address update and store & address update. th ese instructions help to speed up data transfers. (2) six-stage pipelined processing ? the m32r-fpu supports six-stage pipelined instruction processing. not just load/store instructions and register-to-register operation instructions, but also floating-point arithmetic instructions and compound instructions such as load & address update and store & address update ar e executed in one cpuclk period (which is equivalent to 12.5 ns when f(cpuclk) = 80 mhz). ? although instructions are supplied to the execution stage in the order in which they were fetched, it is possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory access, the subsequent register-to-register operation in struction will be executed before that instruction. using such a facility, which is known as the ?out-o f-order-completion? mechanis m, the m32r-fpu is able to control instruction execution without wasting clock cycles. (3) compact instruction code ? the m32r-fpu supports two instruction formats: one 16 bits long, and one 32 bits long. use of the 16-bit instruction format especially helps to suppress the code size of a program. ? moreover, the availability of 32-bit instructions makes programming easier and provides higher performance at the same clock speed than in arch itectures where the address space is segmented. for example, some 32-bit instructions allow control to jump to an addr ess 32 mbytes forward or backward from the currently executed address in on e instruction, making programming easy.
rev.1.00 dec 01, 2004 page 3 of 12 rej03b0116-0100z 32186 group 1.1 outline of the 32186 group 1.1.2 built-in mult iplier/accumulator (1) built-in high-speed multiplier ? the m32r-fpu contains a 32 bits 16 bits high-speed multiplier which enables the m32r-fpu to execute a 32 bits 32 bits integral multiplication instruction in three cpuclk periods. (2) dsp-comparable multiply-accumulate instructions ? the m32r-fpu supports the following four types of multiply-accumulate instru ctions (or multiplication instructions) which each can be executed in one cpuclk pe riod using a 56-bit accumulator. (1) 16 high-order bits of register 16 high-order bits of register (2) 16 low-order bits of register 16 low-order bits of register (3) all 32 bits of register 16 high-order bits of register (4) all 32 bits of register 16 low-order bits of register ? the m32r-fpu has some special instru ctions to round the va lue stored in the accumu lator to 16 or 32 bits or shift the accumulator value before storing in a re gister to have its digits adjusted. because these instructions too are executed in one cpuclk period , when used in combination with high-speed data transfer instructions such as load & address update or store & addr ess update, they enable the m32r- fpu to exhibit superior data processing capability comparable to that of a dsp. 1.1.3 built-in single-precision fpu ? the m32r-fpu supports single-precision floating- point arithmetic fully compliant with ieee 754 standards. specifically, five exce ptions specified in ieee 754 standards (inexact, underflow, division by zero, overflow and invalid operation) and four roundi ng modes (round to nearest, round toward 0, round toward + infinity and round towa rd ? infinity) are suppo rted. what?s more, because general-purpose registers are used to perform floating-point arithmetic, the overhead associated with transferring the operand data can be reduced. 1.1.4 built-in flash memory and ram ? the 32186 contains a ram that can be accessed with zero wait state, allowing to design a high-speed embedded system. ? the internal flash memory can be written to while mounted on a printe d circuit board (on-board writing). use of flash memory facilitates development work, b ecause the chip used at th e development stage can be used directly in mass-production, allowing for a smooth transition from prototype to mass-production without the need to change the printed circuit board. ? the internal flash memory can be rewritten as many as 100 times. ? the internal flash memory has a virtual flash em ulation function, allowing the internal ram to be superficially mapped into part of the internal flas h memory. when combined with the internal real-time debugger (rtd) and the m32r family?s common debu g interface (scalable debug interface or sdi), this function makes the rom table data tuning easy. ? the internal ram can be accessed for reading or rewriting data from an external device independently of the m32r-fpu by using the real-time debugger. the ex ternal device is commun icated using the real- time debugger?s exclusive clock-synchronous serial interface.
rev.1.00 dec 01, 2004 page 4 of 12 rej03b0116-0100z 32186 group 1.1 outline of the 32186 group 1.1.5 built-in clock frequency multiplier ? the 32186 contains a clock frequency multiplier, which is schematically shown in figure 1.1.1 below. figure 1.1.1 conceptual diagram of the clock frequency multiplier 1.1.6 powerful peripher al functions built-in (1) 8-level interrupt controller (icu) (2) 10-channel dmac (3) 55-channel multijunction timers (mjt) (4) 16-channel a/d converter (adc) (5) 6-channel serial interface (sio) (6) 2-channel full-can (7) direct ram interface (dri) (8) real-time debugger (rtd) (9) non-break debug (nbd) (10) wait controller (11) m32r family?s common debug function (scalable debug interface or sdi) table 1.1.1 clock functional block features cpuclk ? cpu clock: defined as f(cpuclk) wh en it indicates the operating clock frequency for the m32r-fpu core, internal flash memory and internal ram. bclk ? peripheral clock: defined as f(bclk) when it indicates the operating clock frequency for the internal peripheral i/o and external data bus. clock output ? bclk pin output: a clock with the same frequency as f(bclk) is output from this pin. ? clkout pin output: a clock with the same or half frequency as f(bclk) is output from this pin. x8 1/4 pll 1/2 clko sel clkout(external bus clock) (20mhz or 10mhz) xin pin (10mhz) bclk (peripheral clock) (20mhz) cpuclk (cpu clock) (80mhz)
rev.1.00 dec 01, 2004 page 5 of 12 rej03b0116-0100z 32186 group 1.2 block diagram 1.2 block diagram figure 1.2.1 shows a block diagram of the 32186. the features of each block are described in table 1.2.1. figure 1.2.1 block diagram of the 32186 m32r-fpu core (max. 80mhz) non-break debug (nbd) direct ram interface (dri) multiplier/accumulator (32 bits x 16 bits + 56 bits) single-precision fpu (fully ieee 754 compliant) internal 32-bit bus internal 32-bit bus internal flash memory (1 mbyte ) internal ram (64 kbytes) pll clock generator internal power supply generator (vdc) address data external bus interface input/output ports, 97 lines real-time debugger (rtd) internal bus interface dmac (10 channels) multijunction timer (mjt: 55 channels) a/d converter (a/d0 : 10-bit converter, 16 channels) serial interface (6 channels) interrupt controller (8 levels) internal 16-bit bus wait controller full can (2 channels)
rev.1.00 dec 01, 2004 page 6 of 12 rej03b0116-0100z 32186 group 1.2 block diagram table 1.2.1 features of the 32186 (1 / 2) functional block features m32r-fpu cpu core ? implementation: si x-stage pipelined instruction processing ? internal 32-bit structure of the core ? register configuration general-purpose regi sters: 32 bits 16 registers control registers: 32 bits 6 registers ? instruction set 16 and 32-bit instruction formats 100 discrete instructions and six addressing modes ? internal multiplier/accumulator (32 bits 16 bits + 56 bits) ? internal single-precision floating-point arithmetic unit (fpu) internal flash memory ? capacity: 1 mbyte (1, 024 kbytes), accessible with one wait state ? durability: rewritable 100 times internal ram ? capacity: 64 kbytes , accessible with zero wait state ? the internal ram can be accessed for reading or rewriting data from the outside independently of the m32r-fpu by usin g the real-time debugger, without ever causing the cpu performance to decrease. bus specification ? fundamental bus cycle: 12.5 ns (when f(cpuclk) = 80 mhz) ? logical address space: 4 gbytes linear ? internal bus specification: internal 32-bit data bus (for cpu <-> internal flash memory and ram access)(or accessed in 64 bits when accessing the internal flash memory for instructions) : internal 16-bit data bus (for internal peripheral i/o access) ? external extension area: during processor mode: maximum 32 mbytes during external extension mode: maximum 31 mbytes (7 mbytes + 8 mbytes 3 blocks) ? external data address: 22-bit address ? external data bus: 16-bit data bus ? shortest external bus access: 1 clkout during read, 1 clkout during write multijunction timer (mjt) ? 55-channel multi-functional timer 16-bit output related timer 11 channel s, 16-bit input/output related timer 10 channels, 16-bit input related timer 8 channels, 32-bit input related timer 8 channels, 16-bit input related up/down time r 2 channels, and 24-bit output related timer 16 channels ? flexible timer configuration is possibl e by interconnecting these timer channels. ? interrupt request: counter underflow or overflow and rising or falling or both edges or high or low level from the tin pin (tin pin can be used as external interrupt inputs irrespective of timer operation.) ? dma transfer request: counter underflow or overflow and rising or falling or both edges or high or low level from the tin pin (tin pin can be used as dma transfer request inputs irrespective of timer operation.) dmac ? number of channels: 10 ? transfers between internal peripheral i/o? s or internal ram?s or between internal peripheral i/o and internal ram are supported. ? capable of advanced dma transfers when us ed in combination with internal peripheral i/o ? transfer request: software or internal peri pheral i/o (a/d converter, mjt, serial interface or can) ? dma channels can be cascaded. (dma transfer on a channel can be started by completion of a transfer on another channel.) ? interrupt request: dma transfer counter register underflow a/d converter (adc) ? 16 channels: 10-bit resolution a/d converter 1 blocks ? conversion modes: in addition to ordinary a/d conversion modes, the adc incorporates comparator mode and 2-channel simultaneous sampling mode. ? operation modes: single conversion mode and n-channel scan mode (n = 1?16) ? sample-and-hold function: performs a/d conversion with the analog input voltages sampled at start of a/d conversion.
rev.1.00 dec 01, 2004 page 7 of 12 rej03b0116-0100z 32186 group 1.2 block diagram a/d converter (adc) ? a/d disconnection detection assist function: suppresses effects of the analog input voltage leakage from the preceding channel during a/d conversion. ? an inflow current bypass circuit is built-in. ? can generate an interrupt or start dma tr ansfer upon completion of a/d conversion. ? either 8 or 10-bit conversion results can be read out. ? interrupt request: completion of a/d conversion ? dma transfer request: completion of a/d conversion serial interface (sio) ? 6-channel serial interface ? can be chosen to be clock-synchronous serial interface or clock-asynchronous serial interface. ? data can be transferred at high speed (2 mb its per second during clock-synchronous mode or 1.25 mbits per second during clock-asynchronous mode when f(bclk) = 20 mhz). ? interrupt request: reception completed, receive error, transmit buffer empty or transmission completed ? dma transfer request: reception comp leted or transmit buffer empty can ? 32 message slots 2 blocks ? compliant with can specification 2.0b active. ? interrupt request: transmissi on completed, reception co mpleted, bus error, error- passive, bus-off or single shot ? dma transfer request: failed to send, tran smission completed or reception completed real-time debugger (rtd) ? internal ram can be rewritten or monitored independently of the cpu by entering a command input from the outside. ? comes with exclusive clock-synchronous serial ports. ? interrupt request: rtd interrupt command input non-break debug (nbd) ? can access to all resources on the address map from the outside ? clock-synchronous parall el interface (4-bit) ? event output function ? ram monitor function direct ram interface (dri) ? can control capture of clock-synchronous parallel data to the internal ram independently of the cpu ? clock-synchronous parallel input (8, 16 or 32-bit) ? maximum transfer rate: 20 mbytes/sec (when f(cpuclk) = 80 mhz). interrupt controller (icu) ? controls interrupt requests fr om the internal peripheral i/o. ? supports 8-level interrupt priority including an interrupt disabled state. ? external interrupt: 27 sour ces (sbi#, tin0, tin3?tin11, tin16?tin27, tin30?tin33) ? tin pin input sensing: rising, falling or both edges or high or low level wait controller ? controls wait states for access to the external extension area. ? insertion of 0?15 wait states by setting up in software + wait state extension by entering wait# signal pll ? a multiply-by-8 clock generating circuit clock ? external input clock fr equency (xin) is 10.0 mhz. ? cpuclk: operating clock for the m32r-fpu co re, internal flash memory and internal ram the cpu clock is 80 mhz (when f(xin) = 10 mhz). ? bclk: operating clock for the internal peripheral i/o and external data bus the peripheral clock is 20 mhz (peripheral module access when f(xin) = 10 mhz). ? bclk pin output: a clock with the same frequency as f(bclk) is output from this pin. ? clkout pin output: a clock with the same or half frequency as f(bclk) is output from this pin. jtag ? boundary scan function vdc ? internal power supply generating circuit: generates the internal power supply from an external power supply (5 or 3.3 v). ports ? input/output pins: 97 pins ? the port input threshold can be set in a program to one of three levels individually for each port group (with or without schmitt circuit, selectable). table 1.2.1 features of the 32186 (2 / 2) functional block features
rev.1.00 dec 01, 2004 page 8 of 12 rej03b0116-0100z 32186 group 1.3 pin functions 1.3 pin functions figure 1.3.1 shows the 32186?s pin function diagr am. pin functions are de scribed in table 1.3.1. figure 1.3.1 pin function diagram 32186 group note 1: mod2 must be connected to the ground (gnd). notes: . the pin (signal) with "#" at the end of the pin name (signal name) indicates it is a low active pin (signal). . : operates with vcce power supply : operates with vcc-bus power supply xin clock multi- junction timer multi- junction timer data bus dri nbd address bus reset port 0 port 1 port 2 port 3 multi- junction timer multi- junction timer serial i/o can address bus bus control bus control/ clock real time debugger port 4 port 7 flash interrupt controller mode a/d converter xout reset# mod0 mod1 16 mod2 (note 1) fp port 6 p61-p63 p70/clkout/wr#/bclk p71/wait# p72/hreq#/tin27 p73/hack#/tin26 p74/rtdtxd/txd3/nbdd0 p75/rtdrxd/rxd3/nbdd1 p76/rtdack/ctx1/nbdd2 p77/rtdclk/crx1/nbdd3 port 8 power supply p82/txd0/to26 p83/rxd0/to25 p84/sclki0/sclko0/to24 p85/txd1/to23 p86/rxd1/to22 p87/ sclki1/sclko1/to21 vcce excvcc vcc-bus vdde excvdd vss sbi# ad0in0-ad0in15 avcc0 avss0 vref0 p93/to16/sclki5/sclko5 p94/to17/txd5/dd15 p96/to19/dd13 p97/to20/dd12 p100/to8 p41/blw#/ble# p42/bhw#/bhe# p43/rd# p44/cs0#/tin8, p45/cs1#/tin9 p46/a13/tin10, p47/a14/tin11 p00/db0/to21/dd0- p07/db7/to28/dd7 p10/db8/to29/dd8- p17/db15/to36/dd15 p20/a23/dd24- p27/a30/dd31 p30/a15/tin4/dd16- p33/a18/tin7/dd19 multi- junction timer serial i/o port 9 multi- junction timer serial i/o serial i/o address bus bus control can serial i/o can serial i/o can/ bus control nbd dri dri dri port 10 port 13 port 15 bus control/ clock address bus/ bus control port 11 port 12 p130/tin16/pwmoff0/din0 p131/tin17/pwmoff1/din1 p132/tin18/din2 p133/tin19/din3 p134/tin20/txd3/din4 p135/tin21/rxd3 p136/tin22/crx1 p137/tin23/ctx1 p150/tin0/clkout/wr# p153/tin3/wait# p95/to18/rxd5/dd14 p107/to15/rxd4/dd0 p110/to0/to29/dd11- p117/to7/to36/dd4 p124/tclk0/a9/dd3 p125/tclk1/a10/dd2 8 8 8 8 4 p34/a19/tin30/dd20- p37/a22/tin33/dd23 4 2 2 3 2 2 6 2 p101/to9/crx0 p102/to10/ctx0 p103/to11/tin24 p104/to12/tin25/dd3 p105/to13/sclki4/sclko4/dd2 p106/to14/txd4/dd1 p126/tclk2/cs2#/dd1 p127/tclk3/cs3#/dd0 port 22 jtag p220/ctx0/hack# p221/crx0/hreq# p224/a11/cs2# jtrst jtms jtck/nbdclk jtdo/nbdevnt# jtdi/nbdsync# p225/a12/cs3# port 17 p174/txd2/to28 p175/rxd2/to27 vccer vcce vcce vcc-bus vcce vcc-bus vcce vcc-bus vcc-bus vcce vcc-bus vcce
rev.1.00 dec 01, 2004 page 9 of 12 rej03b0116-0100z 32186 group 1.3 pin functions table 1.3.1 description of pin functions (1 / 3) type pin name signal name input/output description power supply vccer internal power supply input ? power supply input for the internal voltage generator circuit (5.0 v 0.5 v or 3.3 v 0.3 v) vcce port/internal peripheral i/o pin power supply input ? power supply input for the port and internal peripheral i/o pins (5.0 v 0.5 v or 3.3 v 0.3 v). apply same voltage to the all vcce pins. vcc-bus port/bus interface pin power supply input ? power supply input for the port and bus interface pins (5.0 v 0.5 v or 3.3 v 0.3 v). apply same voltage to the all vcc-bus pins. vdde ram power supply ? backup power supply input for the internal ram (5.0 v 0.5 v or 3.3 v 0.3 v). vss ground ? connect all vss pins to ground (gnd). excvcc vccer control ? this pin connects an external capacitor for the internal voltage generator circuit. excvdd vdde control ? this pin connects an external capacitor for the internal power supply of the internal ram. clock xin, xout clock input clock output input output these are clock input/output pins. a pll-based 8 frequency multiplier is included, which accepts as input a clock whose frequency is 1/8 of the internal cpu clock frequency. (xin input is 10 mhz when f(cpuclk) = 80 mhz.) clkout, bclk system clock output the clkout pin outputs a clock that is equal to the external input clock frequency, xin (i.e., clkout output is 10 mhz when f(cpuclk) = 80 mhz), or two times of xin (i.e.,clkout output is 20 mhz when f(cpuclk) = 80 mhz). this clock is used when operations are synchronous external to the chip. the bclk pin outputs a clock that is two times the external input clock frequency, xin (i.e., bclk output is 20 mhz when f(cpuclk) = 80 mhz). reset reset# reset input reset in put pin for the internal circuit. mode mod0 ? mod2 mode input set the microcomputer?s operation mode. mod0 mod1 mod2 mode l l l single-chip mode l h l external extension mode h l l processor mode (boot mode) (note 1) h h l (settings inhibited) x x h (settings inhibited) x: don?t care flash fp flash protect input this special pin protects the flash memory against rewrites in hardware. address bus a9?a30 address bus output twenty-two address lines (a9?a30) are included, allowing four blocks each up to 8 mb memory space to be connected exte rnal to the chip. a31 is not output. note 1: boot mode requires that the fp pin should be at the high level.
rev.1.00 dec 01, 2004 page 10 of 12 rej03b0116-0100z 32186 group 1.3 pin functions data bus db0?db15 data bus input/output this 16-bit data bus is used to connect external devices. when writing in byte units during a write cycle, the output data at the invalid byte position is undefined. during a read cycle, data on the entire 16-bit bus is always read in. however, only the data at the valid byte position is transferred into the internal circuit. bus control cs0#?cs3# chip select output these are chip select signals for external devices. rd# read output this signal is output when reading an external device. wr# write output this signal is ou tput when writing to an external device. bhw#/blw# byte high/low write output when wr iting to an external device, this signal indicates the valid byte position to which data is transferred. bhw# and blw# correspond to the upper address side (bits 0?7 are valid) and the lower address side (bits 8?15 are valid), respectively. bhe# byte high enable output during an external device access, this signal indicates that the high-order data (bits 0?7) is valid. ble# byte low enable output during an external device access, this signal indicates that the low-order data (bits 8?15) is valid. wait# wait input when accessing an external device, a low-level input on wait# pin extends the wait cycle. hreq# hold request input th is input pin is used by an external device to request control of the external bus. a low-level input on hreq# pin places the cpu in a hold state. hack# hold acknowledge output this signal notifies that the cpu has entered a hold state and relinquished control of the external bus. multijunction timer tin0, tin3?tin11, tin16?tin27, tin30?tin33 timer input input input pins for the multijunction timer. to0?to36 timer output output output pins for the multijunction timer. tclk0 ?tclk3 timer clock input clock input pins for the multijunction timer. a/d converter avcc0 analog power supply input ? avcc0 is the power supply input for the a/d0 converter. connect avcc0 to the power supply rail. avss0 analog ground ? avss0 is the analog ground for the a/d0 converter. connect avss0 to ground. ad0in0 ?ad0in15 analog input input 16-channel analog input pins for the a/d0 converter. vref0 reference voltage input input vref0 is the reference voltage input pin for the a/ d0 converter. interrupt controller sbi# system break interrupt input this is the system break interrupt (sbi) input pin for the interrupt controller. serial interface sclki0/sclko0, sclki1/sclko1, sclki4/sclko4, sclki5/sclko5 uart transmit/ receive clock output or csio transmit/ receive clock input/ output input/output when in uart mode: this pin outputs a clock derived from brg output by dividing it by 2. when in csio mode: this pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected. txd0 ? txd5 transmit data output transmit data output pin for serial interface. rxd0 ? rxd5 received data input received data input pin for serial interface. table 1.3.1 description of pin functions (2 / 3) type pin name signal name input/output description
rev.1.00 dec 01, 2004 page 11 of 12 rej03b0116-0100z 32186 group 1.3 pin functions note 1: input/output ports 5, 14, 16 and 18 ? 21 are nonexistent. note 2: p221 is input-only port. real-time debugger (rtd) rtdtxd rtd transmit data output serial data output pin for the real-time debugger. rtdrxd rtd received data input serial data input pin for the real-time debugger. rtdclk rtd clock input input serial data transmit/receive clock input pin for the real-time debugger. rtdack rtd acknowledge output a low-level pulse is output from this pin synchronously with the start clock for the real-time debugger?s serial data output word. the low-level pulse width indicates the type of command/data received by the real-time debugger. can ctx0, ctx1 transmit data output this pin outputs data from the can module. crx0, crx1 received data input this pin accepts as input the data for the can module. jtag jtms test mode select input test mode se lect input to control the state transition of the test circuit. jtck test clock input clock input for the debug module and test circuit. jtrst test reset input test reset in put to initialize the test circuit asynchronously with device operation. jtdi test data input input this pin accepts as input the test instruction code or test data that is serially received. jtdo test data output output this pin out puts the test instruction code or test data serially. nbd nbdd0 ?nbdd3 command/address/ data input/output nbd command, address, and data input/output pins. nbdclk synchronizing clock input input nbd synchronizing clock input pin. nbdsync# top of data input input this pin controls the start position of nbd data. nbdevnt# event output output this pin is used for event output when an nbd event occurs. dri dd0?dd31 dd input input dri data input pin. din0?din4 din input input dri event input pin. input/output ports (note 1) p00?p07 input/output port 0 input/output programmable input/output port. p10?p17 input/output port 1 input/output p20?p27 input/output port 2 input/output p30?p37 input/output port 3 input/output p41?p47 input/output port 4 input/output p61?p63 input/output port 6 input/output p70?p77 input/output port 7 input/output p82?p87 input/output port 8 input/output p93?p97 input/output port 9 input/output p100?p107 input/output port 10 input/output p110?p117 input/output port 11 input/output p124?p127 input/output port 12 input/output p130?p137 input/output port 13 input/output p150, p153 inpu t/output port 15 input/output p174, p175 inpu t/output port 17 input/output p220, p221 (note 2), p224, p225 input/output port 22 input/output table 1.3.1 description of pin functions (3 / 3) type pin name signal name input/output description
rev.1.00 dec 01, 2004 page 12 of 12 rej03b0116-0100z 32186 group 1.4 pin assignments 1.4 pin assignments figure 1.4.1 shows the 32186?s pin assignment diagram. figure 1.4.1 pin assignment diagram (top view) 32186 group 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 vss p87/sclki1/sclko1/to21 p86/rxd1/to22 p85/txd1/to23 p84/sclki0/sclko0/to24 p83/rxd0/to25 p82/txd0/to26 vccer p175/rxd2/to27 p174/txd2/to28 vss excvcc avss0 ad0in15 ad0in14 ad0in13 ad0in12 ad0in11 ad0in10 ad0in9 ad0in8 ad0in7 ad0in6 ad0in5 ad0in4 ad0in3 ad0in2 ad0in1 ad0in0 avcc0 vref0 p17/db15/to36/dd15 p16/db14/to35/dd14 p15/db13/to34/dd13 p14/db12/to33/dd12 p13/db11/to32/dd11 p221/crx0/hreq# p225/a12/cs3# vss xin xout vcc-bus p224/a11/cs2# p30/a15/tin4/dd16 p31/a16/tin5/dd17 p32/a17/tin6/dd18 p33/a18/tin7/dd19 p34/a19/tin30/dd20 p35/a20/tin31/dd21 p36/a21/tin32/dd22 p37/a22/tin33/dd23 p20/a23/dd24 p21/a24/dd25 p22/a25/dd26 p23/a26/dd27 vcc-bus vss p24/a27/dd28 p25/a28/dd29 p26/a29/dd30 p27/a30/dd31 p00/db0/to21/dd0 p01/db1/to22/dd1 p02/db2/to23/dd2 p03/db3/to24/dd3 p04/db4/to25/dd4 p05/db5/to26/dd5 p06/db6/to27/dd6 p07/db7/to28/dd7 p10/db8/to29/dd8 p11/db9/to30/dd9 p12/db10/to31/dd10 jtms jtck/nbdclk jtrst jtdo/nbdevnt# jtdi/nbdsync# p103/to11/tin24 p104/to12/tin25/dd3 p105/to13/sclki4/sclko4/dd2 p106/to14/txd4/dd1 p107/to15/rxd4/dd0 p124/tclk0/a9/dd3 p125/tclk1/a10/dd2 p126/tclk2/cs2#/dd1 p127/tclk3/cs3#/dd0 mod2(note 1) p130/tin16/pwmoff0/din0 p131/tin17/pwmoff1/din1 p132/tin18/din2 p133/tin19/din3 p134/tin20/txd3/din4 p135/tin21/rxd3 p136/tin22/crx1 p137/tin23/ctx1 vcce p150/tin0/clkout/wr# p153/tin3/wait# p41/blw#/ble# p42/bhw#/bhe# excvcc vss p43/rd# p44/cs0#/tin8 p45/cs1#/tin9 p46/a13/tin10 p47/a14/tin11 p220/ctx0/hack# vdde p102/to10/ctx0 p101/to9/crx0 p100/to8 p117/to7/to36/dd4 p116/to6/to35/dd5 p115/to5/to34/dd6 p114/to4/to33/dd7 p113/to3/to32/dd8 p112/to2/to31/dd9 p111/to1/to30/dd10 p110/to0/to29/dd11 vss vcce fp mod1 mod0 reset# p97/to20/dd12 p96/to19/dd13 p95/to18/rxd5/dd14 p94/to17/txd5/dd15 p93/to16/sclki5/sclko5 p77/rtdclk/crx1/nbdd3 p76/rtdack/ctx1/nbdd2 p75/rtdrxd/rxd3/nbdd1 p74/rtdtxd/txd3/nbdd0 p73/hack#/tin26 p72/hreq#/tin27 p71/wait# p70/clkout/wr#/bclk sbi# p63 p62 p61 excvdd package: 144p6q-a(0.5-mm pitch) note 1: mod2 must be connected to the ground (gnd). note: ? the symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low.
rev.0.01 sep 21, 2004 page 13 of 14 rej03b0116-0001z 32186 group 2.1 outline of the address space 2.1 outline of the address space the logical addresses of the m32r are always handled in 32 bits, providing a linear address space of up to 4 gbytes. the address space of the m32r/ecu consists of the following: (1) user space ? internal rom area ? external extension area ? internal ram area ? sfr (special function register) area the 2 gbytes from the address h?0000 0000 to the address h?7fff ffff comprise th e user space. located in this space are the internal rom area, an external extension area, the internal ram area and the sfr (special function register) area (in which a set of internal peri pheral i/o registers exist). of these, the internal rom and external extension areas are located differently depe nding on mode settings as will be described later. (2) system space (not open to the user) the 2 gbytes from th e address h?8000 00 00 to the address h?ffff ffff co mprise the syst em space. this space (except for sfr area for nbd control) is reserved for use by development tools such as an in-circuit emulator and debug monitor. 2.2 operation modes the microcomputer is placed in one of the followi ng modes depending on how cpu operation mode is set by mod0 and mod1 pins. note 1: connect vcce and vss to the vcce i nput power supply and ground, respectively. the internal rom and external extens ion areas are located differently depe nding on how operation mode is set. (all other areas in the address space are located the same way.) the foll owing diagram shows how the internal rom and external extension areas are mapped into the address space in each operation mode. table 2.2.1 operation mode settings mod0 mod1 mod2 (note 1) operation mode vss vss vss single-chip mode vss vcce vss external extension mode vcce vss vss processor mode (fp = vss) vcce vcce vss (settings inhibited) ? ? vcce (settings inhibited)
rev.0.01 sep 21, 2004 page 14 of 14 rej03b0116-0001z 32186 group 2.2 operation modes figure 2.2.1 address space logical address single chip mode external extension mode processor mode logical address (64 mbyte) cs3 area (8 mbyte) sfr area (16 kbyte) internal ram area (64 kbyte) h'0000 0000 h'7fff ffff h'0000 0000 h'ffff ffff h'8000 0000 h'007f ffff h'0080 0000 h'0010 0000 h'0080 4000 h'0081 3fff h'0081 4000 h'00ff ffff h'03ff ffff h'0380 0000 h'037f ffff h'0300 0000 h'02ff ffff h'0280 0000 h'027f ffff h'0200 0000 h'01ff ffff h'0180 0000 h'017f ffff h'0100 0000 h'000f ffff h'0080 3fff internal rom area (1 mbyte) note: cs0?cs3 areas: extension areas of up to 32 mbytes user space system space 2 gbytes 2 gbytes cs3 area (8 mbyte) cs2 area (8 mbyte) cs2 area (8 mbyte) cs1 area (8 mbyte) cs1 area (8 mbyte) cs0 area (8 mbyte) cs0 area (7 mbyte) internal rom area (1 mbyte) sfr area (16 kbyte) internal ram area (64 kbyte) (64 mbyte) (64 mbyte) (64 mbyte) ghost area in 64-mbyte units sfr area (16 kbyte) internal ram area (64 kbyte) h'e000 0000 nbd control
rev.0.01 sep 21, 2004 page 15 of 16 rej03b0116-0001z 32186 group 3.1 outline of the interrupt controller 3.1 outline of the interrupt controller the interrupt controller (icu) manages maskable interr upts from internal peripheral i/os and a system break interrupt (sbi). the maskable interrupts from internal pe ripheral i/os are sent to the m32r cpu as external interrupts (ei). the maskable interrupts from internal peripheral i/os ar e managed by assigning them one of eight priority levels including an interrupt-disabled state. if two or more interrupt requests with the same priority level occur at the same time, their priorities are resolved by predetermined hardware priority. the source of an interrupt request generated in internal peripheral i/os is identified by r eading the relevant interrupt status register provided for internal peripheral i/os. on the other hand, the system break interrupt (sbi) is r ecognized when a low-going tr ansition occurs on the sbi# signal input pin. this interrupt is used for emergency purp oses such as when power outage is detected or a fault condition is notified by an external watchdog tim er, so that it is always accepted irrespective of the psw register ie bit status. when the cpu has finished servicing an sbi, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. specifications of the interrupt controller are outlined below. note 1: there are actually 256 interrupt request resources in total when counted individually, which are grouped into 40 interrupt request resources. table 3.1.1 outline of the interrupt controller (icu) item specification interrupt request source maskable interrupt requests from internal peripheral i/os: 40 sources (note 1) system break interrupt request: 1 source (entered from sbi# pin) priority management 8 priority levels including an interrupt-disabled state (however, interrupts with the same priority level have their priorities resolved by fixed hardware priority.)
rev.0.01 sep 21, 2004 page 16 of 16 rej03b0116-0001z 32186 group 3.1 outline of the interrupt controller figure 3.1.1 block diagram of the interrupt controller interrupt vector register (ivect) interrupt request mask register (imask) new_imask external interrupt (ei) request generated (maskable) imask compari- son ilevel system break interrupt (sbi) request generated (nonmaskable) sbi# ei sbi interrupt controller interrupt control register sbi control register (sbicr) sbireq ireq ireq ireq ireq ireq ireq peripheral circuits edge interrupt control circuit edge edge level interrupt request interrupt request interrupt request level level to the cpu core to the cpu core interrupt control circuit interrupt control circuit priority resolved by interrupt priority levels set priority resolved by fixed hardware priority
rev.0.01 sep 21, 2004 page 17 of 22 rej03b0116-0001z 32186 group 4.1 outline of input/output ports 4.1 outline of input/output ports the 32186 has a total of 97 input/output ports from p0?p13, p15, p17 and p22 (except p5, which is reserved for future use). these input/output ports can be used as input or output ports by setting the respective direction registers. each input/output port has double or triple functions sh ared with other internal pe ripheral i/o or external bus interface related signal lines, or mult iple functions shared with multi-function peripheral i/os. pin functions are selected depending on the operation mode of the cpu or by setting the operation mo de register and peripheral function select register for the input/output port. (if any internal peripheral i/o has still another function, it is also necessary to set the register provide d for that internal peripheral i/o.) abundant port functions are incorporated, including a port input level switching function, port output drive capability setting function, and noise canceller control function. note that before any ports can be used in input mode, th is port input function enable bit must be set accordingly. the input/output ports are outlined below. note : ? p5, p14, p16, p18-p21 are nonexist. table 4.1.1 outline of input/output ports item specification number of ports total 97 ports p0 : p1 : p2 : p3 : p4 : p6 : p7 : p8 : p9 : p10 : p11 : p12 : p13 : p15 : p17 : p22 : p00?p07 (8 ports) p10?p17 (8 ports) p20?p27 (8 ports) p30?p37 (8 ports) p41?p47 (7 ports) p61?p63 (3 ports) p70?p77 (8 ports) p82?p87 (6 ports) p93?p97 (5 ports) p100?p107 (8 ports) p110?p117 (8 ports) p124?p127 (4 ports) p130?p137 (8 ports) p150, p153 (2 ports) p174, p175 (2 ports) p220, p221, p224, p225 (4 ports) port function the input/output ports can individually be set for input or output mode using the direction control register provided for each input/outpu t port. (however, p221 is an input-only port.) pin function shared with peripheral i/o or external bus interface signals to serve dual-functions (or shared with two or more peripheral i/o functions to serve multiple functions)
rev.0.01 sep 21, 2004 page 18 of 22 rej03b0116-0001z 32186 group 4.2 selecting pin functions 4.2 selecting pin functions each input/output port serves dual functions sharing the pin with other internal peripheral i/o or external bus interface signal lines (or multiple functions sharing the pin with two or more peripheral i/o functions). pin functions are selected depending on the operation mode of the cpu or by setting the operation mode register and peripheral function select register for the input/output port. p0?p4, p124, p125, p224 and p225, when the cpu is set to operate in processor mode, all are switched to serve as signal pins for exte rnal access. the cpu operation mode is determined dependin g on how the mod0 and mod1 pins are set (see the table below). note 1: p41?p43 only function as external bus interface signal pins. note : ? vcce and vss are connected to ma in power supply and gnd, respectively. each input/output port has their functions switched between input/output port pins and internal peripheral i/o pins by setting the respective port operation mode and peripheral func tion select registers. if any internal peripheral i/o has two or more pin functions, use the register provided for that internal peripheral i/o to select the desired pin function. note that fp and mod1 pin operations during internal flash memory programming do not affect the pin functions. table 4.2.1 cpu operation modes and p0?p4, p124, p125, p224 and p225 pin functions mod0 mod1 operation mode p0?p4, p124, p125, p224 and p225 pin function vss vss single-chip mode input/output port pin vss vcce external extension mode input/output port or external bus interface signal pin (note 1) vcce vss processor mode external bus interface signal pin vcce vcce (settings inhibited) ?
rev.0.01 sep 21, 2004 page 19 of 22 rej03b0116-0001z 32186 group 4.2 selecting pin functions figure 4.2.1 input/output ports and pin func tion assignments during single chip mode 0 1 2 3 4 5 6 7 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 tin16 / tin17 / tin20 / tin18 / tin19 / tin21 / tin22 / tin23 / pwmoff0 / pwmoff1 / txd3 / din2 din3 rxd3 crx1 ctx1 din0 din1 din4 to21 / to22 / to23 / to24 / to25 / to26 / to27 / to28 / dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 clkout / rtdtxd / rtdrxd / rtdack / rtdclk / hreq# / hack# / wr# / wait# txd3 / rxd3 / ctx1 / crx1 / tin27 tin26 bclk( note 2) nbdd0 nbdd1 nbdd2 nbdd3 to29 / to30 / to31 / to32 / to33 / to34 / to35 / to36 / dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 tclk0 / tclk1 / tclk2 / tclk3 / dd3 dd2 dd1 dd0 tin0 / tin3 / clkout / wait# wr#( note 2) to0 / to1 / to2 / to3 / to4 / to5 / to6 / to7 / to29 / to30 / to31 / to32 / to33 / to34 / to35 / to36 / dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 tin4 / tin5 / tin6 / tin7 / tin30 / tin31 / tin32 / tin33 / dd16 dd17 dd18 dd19 dd20 dd21 dd22 dd23 to12 / to14 / to15 / to9 / to10 / to11 / to8 tin25 / txd4 / rxd4 / crx0 ctx0 tin24 dd3 dd1 dd0 to13 / sclki4 / sclko4 dd2 sclki0 / sclki1 / mod0 mod1 txd0 / rxd0 / txd1 / rxd1 / sclko0 / sclko1 / ( note 1) ( note 1) to26 to25 to23 to22 to24 to21 to16 / to17 / to18 / to19 / to20 / sclki5 / txd5 / rxd5 / dd13 dd12 sclko5 dd15 dd14 dd24 dd25 dd26 dd27 dd28 dd29 dd30 dd31 p41 p42 p43 tin8 tin9 tin10 tin11 ( port only) ( port only) ( port only) p61 p62 p63 sbi# ( port only) ( port only) ( port only) ( note 1) txd2 / rxd2 / to28 to27 ctx0 / crx0 / p224 p225 hack# hreq# ( port only) ( port only) pin functions are selected by the settings for the port operation mode and port peripheral function select registers pin functions are selected by the settings for the port operation mode, port peripheral function select and nbd function select registers note 1: these ports cannot be used for input/output port function. the sbi#, mod0 and mod1 pin input levels can be read from th ese ports. note 2: respective functions are selected by the bus mode control register. note : p5, p14, p16, p18, p19, p20 and p21 are not provided.
rev.0.01 sep 21, 2004 page 20 of 22 rej03b0116-0001z 32186 group 4.2 selecting pin functions figure 4.2.2 input/output ports and pin function assignments during external extension mode 0 1 2 3 4 5 6 7 p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 tin16 / tin17 / tin20 / tin18 / tin19 / tin21 / tin22 / tin23 / pwmoff0 / pwmoff1 / txd3 / din2 din3 rxd3 crx1 ctx1 din0 din1 din4 db0 / db1 / db2 / db3 / db4 / db5 / db6 / db7 / to21 / to22 / to23 / to24 / to25 / to26 / to27 / to28 / dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 blw# / bhw# / rd# cs0# / cs1# / a13 / a14 / ble# bhe# ( note 1) tin8 tin9 tin10 tin11 ( note 1, 3) ( note 1, 3) clkout / rtdtxd / rtdrxd / rtdack / rtdclk / hreq# / hack# / wr# / wait# txd3 / rxd3 / ctx1 / crx1 / tin27 tin26 bclk (note 3) nbdd0 nbdd1 nbdd2 nbdd3 db8 / db9 / db10 / db11 / db12 / db13 / db14 / db15 / to29 / to30 / to31 / to32 / to33 / to34 / to35 / to36 / dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 tclk0 / tclk1 / tclk2 / tclk3 / a9 / a10 / cs2# / cs3# / dd3 dd2 dd1 dd0 tin0 / tin3 / clkout / wait# wr# (note 3) to0 / to1 / to2 / to3 / to4 / to5 / to6 / to7 / to29 / to30 / to31 / to32 / to33 / to34 / to35 / to36 / dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 a15 / a16 / a17 / a18 / a19 / a20 / a21 / a22 / tin4 / tin5 / tin6 / tin7 / tin30 / tin31 / tin32 / tin33 / dd16 dd17 dd18 dd19 dd20 dd21 dd22 dd23 to12 / to14 / to15 / to9 / to10 / to11 / to8 tin25 / txd4 / rxd4 / crx0 ctx0 tin24 dd3 dd1 dd0 to13 / sclki4 / sclko4 dd2 sclki0 / sclki1 / mod0 mod1 txd0 / rxd0 / txd1 / rxd1 / sclko0 / sclko1 / (note 2) (note 2) to26 to25 to23 to22 to24 to21 to16 / to17 / to18 / to19 / to20 / sclki5 / txd5 / rxd5 / dd13 dd12 sclko5 dd15 dd14 a23 / a24 / a25 / a26 / a27 / a28 / a29 / a30 / dd24 dd25 dd26 dd27 dd28 dd29 dd30 dd31 p61 p62 p63 sbi# (port only) (port only) (port only) (note 2) txd2 / rxd2 / to28 to27 ctx0 / crx0 / a11 / a12 / hack# hreq# cs2# cs3# note 1: these ports cannot be used for input/output port function, function as external bus interface related signals. note 2: these ports cannot be used for input/output port function. the sbi#, mod0 and mod1 pin input levels can be read from th ese ports. note 3: respective functions are selected by the bus mode control register. note : p5, p14, p16, p18, p19, p20 and p21 are not provided. pin functions are selected by the settings for the port operation mode and port peripheral function select registers pin functions are selected by the settings for the port operation mode, port peripheral function select and nbd function select registers
rev.0.01 sep 21, 2004 page 21 of 22 rej03b0116-0001z 32186 group 4.2 selecting pin functions figure 4.2.3 input/output ports and pin function assignments during processor mode p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21 p22 (note 1) tin16 / tin17 / tin20 / tin18 / tin19 / tin21 / tin22 / tin23 / pwmoff0 / pwmoff1 / txd3 / din2 din3 rxd3 crx1 ctx1 din0 din1 din4 db0 db1 db2 db3 db4 db5 db6 db7 clkout / rtdtxd / rtdrxd / rtdack / rtdclk / hreq# / hack# / wr# / wait# txd3 / rxd3 / ctx1 / crx1 / tin27 tin26 bclk( note 3) nbdd0 nbdd1 nbdd2 nbdd3 db8 db9 db10 db11 db12 db13 db14 db15 tclk2 / tclk3 / a9 a10 cs2# / cs3# / (note 1) (note 1) dd1 dd0 tin0 / tin3 / clkout / wait# wr#( note 3) to0 / to1 / to2 / to3 / to4 / to5 / to6 / to7 / to29 / to30 / to31 / to32 / to33 / to34 / to35 / to36 / dd11 dd10 dd9 dd8 dd7 dd6 dd5 dd4 a15 a16 a17 a18 a19 a20 a21 a22 to12 / to14 / to15 / to9 / to10 / to11 / to8 tin25 / txd4 / rxd4 / crx0 ctx0 tin24 dd3 dd1 dd0 to13 / sclki4 / sclko4 dd2 sclki0 / sclki1 / mod0 mod1 txd0 / rxd0 / txd1 / rxd1 / sclko0 / sclko1 / (note 2) (note 2) to26 to25 to23 to22 to24 to21 to16 / to17 / to18 / to19 / to20 / sclki5 / txd5 / rxd5 / dd13 dd12 sclko5 dd15 dd14 a23 a24 a25 a26 a27 a28 a29 a30 blw# / bhw# / rd# cs0# cs1# a13 a14 ble#( note 3) bhe#( note 3) p61 p62 p63 sbi# ( port only) ( port only) ( port only) (note 2) txd2 / rxd2 / to28 to27 ctx0 / crx0 / a11/cs2# a12/cs3# hack# hreq# (note 1) (note 1) pin functions are selected by the settings for the port operation mode, port peripheral function select and nbd function select registers note 1: these ports cannot be used for input/output port function, function as external bus interface related signals. note 2: these ports cannot be used for input/output port function. the sbi#, mod0 and mod1 pin input levels can be read from th ese ports. note 3: respective functions are selected by the bus mode control register. note : p5, p14, p16, p18, p19, p20 and p21 are not provided. 0 1 2 3 4 5 6 7
rev.0.01 sep 21, 2004 page 22 of 22 rej03b0116-0001z 32186 group 4.3 port input level switching function 4.3 port input level switching function the port input level switching function allows the port thre shold to be switched to one of three voltage levels (with or without schmitt as selected) in units of the following port group. this can be set to the following registers in units of group. note that port inputs are us ed for the dd input of dri. port group 0: p00?p07, p10?p17, p20?p27, p30?p37, p41?p47, p70?p73, p224, p225 port group 1: p82?p87, p174, p175 port group 3: p93?p97, p110?p117 port group 4: p124?p127 port group 5: p61?p63, sbi# port group 6: p74?p77, p100?p107 port group 7: p220, p221 port group 8: p130?p137, p150, p153 figure 4.3.1 port input level switching function vt+ vt- 0.7vcce 0.5vcce 0.35vcce cmos s s s s s wfnsel ptnsel vtnsel standard input level for each peripheral function pin schmitt peripheral function input port input pin threshold input function enable noise canceller s
rev.0.01 sep 21, 2004 page 23 of 23 rej03b0116-0001z 32186 group 5.1 outline of the dmac 5.1 outline of the dmac the microcomputer internally contains a 10-channel dmac (direction me mory access controller). it allows data to be transferred at high speed between internal peripheral i/os, between internal ram and internal peripheral i/o, or between internal rams, as initiated by a software trigger or requested from an internal peripheral i/o. note 1: the dma channels can be cascaded in the manner described below. ? start dma transfer on dma1 upon completion of one dma transfer on dma0 ? start dma transfer on dma5 upon completion of all dma transfers on dma0 (upon underflow of the transfer count register) ? start dma transfer on dma2 upon completion of one dma transfer on dma1 ? start dma transfer on dma0 upon completion of one dma transfer on dma2 ? start dma transfer on dma3 upon completion of one dma transfer on dma2 ? start dma transfer on dma4 upon completion of one dma transfer on dma3 ? start dma transfer on dma6 upon completion of one dma transfer on dma5 ? start dma transfer on dma7 upon completion of one dma transfer on dma6 ? start dma transfer on dma5 upon completion of one dma transfer on dma7 ? start dma transfer on dma8 upon completion of one dma transfer on dma7 ? start dma transfer on dma9 upon completion of one dma transfer on dma8 note 2: the source address and destination address cannot go over the bank, which can be only transferred to the same bank or another one from a certain bank. table 5.1.1 outline of the dmac item description number of channels 10 channels transfer request sources ? software trigger ? request from internal peripheral i/os: a/d converter, multijunction timer, serial interface (reception completed, tr ansmit buffer empty), can or dri ? dma channels can be cascaded (note 1) maximum number of times transferred 65,536 times transferable address space (note 2) ? 64 kbytes + 16 kbytes (address space from h?0080 0000 to h?0081 3fff) ? transfers between internal peripheral i/os, between internal ram and internal peripheral i/o, and between internal rams are supported. transfer data size 16 or 8 bits transfer method single transfer dma (control of the internal bus is relinquished for each transfer performed), dual address transfer transfer mode single transfer mode direction of transfer one of three modes ca n be selected for the source and destination: ? address fixed ? address incremental ? ring buffered (can be selected from 32, 16, 8, 4 or 2 times) channel priority dma0 > dma1 > dma2 > dma3 > dma4 > dma5 > dma6 > dma7 > dma8 > dma9 (priority is fixed) maximum transfer rate 13.3 mbytes per second (when internal peripheral clock bclk = 20 mhz) interrupt request group interrupt request can be generated when each transfer count register underflows. transfer area (note 2) 64 kbytes +16 kbytes from h? 0080 0000 to h?0081 3fff (transferable in the entire ram/sfr area)
rev.0.01 sep 21, 2004 page 24 of 28 rej03b0116-0001z 32186 group 6.1 outline of multijunction timers 6.1 outline of multijunction timers the multijunction timers (abbreviated mjt) have input event and output event buses. therefore, in addition to being used as a single unit, the timers can be internally connected to each other. this capability allows for highly flexible timer configuration, making it possible to meet various application needs. it is because the timers are connected to the internal event buses at multiple points that they are called the ?multijunction? timers. the 32186 has six types of mjt as listed in the table below, providing a total of 55-channel timers. table 6.1.1 outline of mjt name type no. of channels description top (timer output) output-related 16-bit timer (down-counter) 11 one of three output modes can be selected by software. ? single-shot output mode ? delayed single-shot output mode ? continuous output mode tio (timer input output) input/output-related 16-bit timer (down-counter) 10 one of three input modes or four output modes can be selected by software. ? measure clear input mode ? measure free-run input mode ? noise processing input mode ? pwm output mode ? single-shot output mode ? delayed single-shot output mode ? continuous output mode tms (timer measure small) input-related 16-bit timer (up-counter) 8 16-bit input measure timer tml (timer measure large) input-related 32-bit timer (up-counter) 8 32-bit input measure timer tid (timer input derivation) input-related 16-bit timer (up/down-counter) 2 one of four input modes can be selected by software. ? fixed period mode ? event count mode ? multiply-by-4 event count mode ? up/down event count mode tou (timer output unification) output-related 24-bit timer (down-counter) (16-bit timer during pwm output and single-shot pwm output modes) 16 one of five output modes can be selected by software. ? pwm output mode ? single-shot pwm output mode ? delayed single-shot output mode ? single-shot output mode ? continuous output mode
rev.0.01 sep 21, 2004 page 25 of 28 rej03b0116-0001z 32186 group 6.1 outline of multijunction timers figure 6.1.1 block diagram of mjt (1/4) tclk0 (p124) tin0 (p150) tin3 (p153) tin4 (p30) tin5 (p31) tin6 (p32) tclk1 (p125) tin7 (p33) tclk2 (p126) tin8 (p44) tin9 (p45) tin10 (p46) tin11 (p47) to0 (p110) to1 (p111) to2 (p112) to3 (p113) to4 (p114) to5 (p115) to6 (p116) to7 (p117) to8 (p100) to9 (p101) to10 (p102) to11 (p103) to12 (p104) to13 (p105) to14 (p106) to15 (p107) to16 (p93) to17 (p94) to18 (p95) to19 (p96) to20 (p97) irq9 irq12 dma1 irq12 irq12 irq12 irq8 dma4 irq8 dma5 irq8 irq8 irq8 irq2 irq2 irq2 irq2 irq2 irq2 irq1 irq1 irq6 irq6 irq5 irq0 irq0 irq0 irq0 irq4 irq4 irq4 irq4 dma0 dma common irq3 : prescalers : output flip-flop : selector notes: irq0-18 denotes interrupt signals, of which the same number represents the same group of interrupts. dma0-9 and dma common denote dma request signals to the dmac. ad0trg denotes trigger signal to the a/d0 converter. s f/f prs0-5 dma common dma3,dma commom irq3 top 0 clk en udf top 1 clk en udf top 2 clk en udf top 3 clk en udf top 4 clk en udf top 5 clk en udf top 6 clk en udf top 7 clk en udf top 8 clk en udf top 9 clk en udf top 10 clk en udf tio 0 clk en/cap udf tio 1 clk en/cap udf tio 2 clk en/cap udf tio 3 clk en/cap udf tio 4 clk en/cap udf tio 5 clk en/cap udf tio 6 clk en/cap udf tio 7 clk en/cap udf tio 8 clk en/cap udf tio 9 clk en/cap udf s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s tin0s tclk0s f/f10 f/f11 f/f12 f/f13 f/f14 f/f15 f/f16 f/f17 f/f18 f/f19 f/f20 f/f0 f/f1 f/f2 f/f3 f/f4 f/f5 f/f6 f/f7 f/f8 f/f9 tin3s tin4s tin5s tin6s s s s prs0 prs1 prs2 tclk1s tin7s tclk2s tin8s tin9s tin10s tin11s s s s 3210 3210 0123 3210 3210 0123 clock bus input event bus output event bus bclk 1/4 1/2
rev.0.01 sep 21, 2004 page 26 of 28 rej03b0116-0001z 32186 group 6.1 outline of multijunction timers figure 6.1.2 block diagram of mjt (2/4) tclk3 (p127) tin16/pwmoff0 (p130) tin17/pwmoff1 (p131) tin18 (p132) tin19 (p133) tin20 (p134) tin21 (p135) tin22 (p136) tin23 (p137) tin30 (p34) tin31 (p35) tin32 (p36) tin33/pwmoff2 (p37) irq10 irq10 irq10 dma2 irq10 dma4 irq11 dma5 irq11 irq11 irq11 (to a/d0 converter) ad0trg irq18 irq18 irq18 irq18 ad0trg (to a/d0 converter) ad0trg (to a/d0 converter) ad0trg (to a/d0 converter) irq7 irq7 bclk 1/4 dma common tms 0 clk cap3 cap2 cap1 cap0 ovf s tclk3s s s s s tms 1 clk cap3 cap2 cap1 cap0 ovf tin16s tin17s tin18s tin19s s s s s s tml 0 (32-bit) clk cap3 cap2 cap1 cap0 tin20s tin21s tin22s tin23s s s s s s tml 1 (32-bit) clk cap3 cap2 cap1 cap0 tin30s tin31s tin32s tin33s s s s s s 3210 3210 0123 3210 3210 0123 clock bus input event bus output event bus 1/2
rev.0.01 sep 21, 2004 page 27 of 28 rej03b0116-0001z 32186 group 6.1 outline of multijunction timers figure 6.1.3 block diagram of mjt (3/4) tin16/pwmoff0 (p130) tin24 (p103) tin25 (p104) tin17/pwmoff1 (p131) tin26 (p73) tin27 (p72) to21 (p00/p87) to22 (p01/p86) to23 (p02/p85) to24 (p03/p84) to25 (p04/p83) to26 (p05/p82) to27 (p06/p175) to28 (p07/p174) to29 (p10/p110) to30 (p11/p111) to31 (p12/p112) to32 (p13/p113) to33 (p14/p114) to34 (p15/p115) to35 (p16/p116) to36 (p17/p117) irq11 irq11 irq11 irq11 dma5 dma6 dma7 dma8 dma9 dma0 dma4 dma1 irq13 irq13 irq13 irq13 irq13 irq13 irq13 irq13 irq14 irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq16 irq15 bclk dma0 dma1 dma3 tou0_0 (24-bit) clk en udf tou0_1 (24-bit) clk en udf tou0_2 (24-bit) clk en udf tou0_3 (24-bit) clk en udf tou0_4 (24-bit) clk en udf tou0_5 (24-bit) clk en udf tou0_6 (24-bit) clk en udf tou0_7 (24-bit) clk en udf tid 0 clk clk1 clk2 ovf udf tou1_0 (24-bit) clk en udf tou1_1 (24-bit) clk en udf tou1_2 (24-bit) clk en udf tou1_3 (24-bit) clk en udf tou1_4 (24-bit) clk en udf tou1_5 (24-bit) clk en udf tou1_6 (24-bit) clk en udf tou1_7 (24-bit) clk en udf tid 1 clk clk1 clk2 ovf udf tin25s pwmoff1s pwmoff0s po1dis po0dis tin24s prs3 f/f29 f/f30 f/f31 f/f32 f/f33 f/f34 f/f35 f/f36 f/f21 f/f22 f/f23 f/f24 f/f25 f/f26 f/f27 f/f28 s tin27s tin26s prs4 s s s output event bus 0 bclk 1/4 1/4
rev.0.01 sep 21, 2004 page 28 of 28 rej03b0116-0001z 32186 group 6.1 outline of multijunction timers figure 6.1.4 block diagram of mjt (4/4) s s s s s s s s s s s dma0 udf end dma1 udf end dma2 udf end dma3 udf end dma4 udf end dma5 udf end dma6 udf end dma7 udf end dma8 udf end dma9 udf end s s s s s s s s s (note 1) tin3s tid1_udf/ovf tou1_1irq (note 2) dri(din1) sio4_rxd tid0_udf/ovf (note 2) can0_s0/s31 tou1_0irq (note 2) dri(din0) (note 2) sio4_txd (note 2) a/d0 conversion completed (note 1) tin0s tio8_udf tin30s tio9_udf (note 2) a/d0 conversion completed tio8_udf software start software start software start (note 1) tin18s software start (note 2) sio0_txd (note 2) sio1_rxd software start (note 2) sio0_rxd software start dma0-4 interrupts dma5-9 interrupts (note 2) sio2_rxd software start (note 2) sio1_txd (note 2) can0_s0/s31 software start (note 2) sio2_txd (note 2) can0_s1/s30 software start (note 2) sio3_rxd (note 2) can0_s1/s30 (note 2) dri(din2) sio5_txd (note 1) tin0s tou1_6irq (note 2) dri(din3) sio5_rxd (note 1) tin19s (note 2) sio0_txd tou1_7irq (note 1) tin7s (note 2) dri(din4) (note 1) tin20s tou0_0irq (note 1) tin8s (note 2) dri(dec0_udf) (note 2) can1_s0/s31 tou0_1irq (note 2) sio1_rxd (note 2) dri address counter 0 transfer completed (note 2) dri(dec1_udf) tou0_6irq (note 2) can1_s0/s31 (note 2) dri latch event counter_udf (note 2) dri(dec3_udf) tou0_7irq (note 2) dri transfer counter_udf (note 2) dri(dec4_udf) (note 2) dri(din5) tou0_2irq (note 2) sio3_txd (note 2) dri address counter 1 transfer completed (note 2) dri(dec2_udf) (note 2) can1_s1/s30 software start (note 2) sio3_txd (note 2) can1_s1/s30 0123 input event bus output event bus 3210 3210 0123 note 1: indicates edge select input at the timer input pin. note 2: indicates an input signal from each peripheral circuit.
rev.0.01 sep 21, 2004 page 29 of 32 rej03b0116-0001z 32186 group 7.1 outline of a/d converter 7.1 outline of a/d converter the 32186 contains 10-bit resolution a/ d converter of the successive approx imation type. the a/d converter has 16 analog input pins (channels) ad0in0?ad0in15. in addition to performing conversion individually on each channel, the a/d converter can perform conversion successive ly on all of n channels (n = 1?16) as a single group. the conversion result can be read out in either 10 or 8 bits. there are following conversion and operation modes for the a/d conversion: (1) conversion modes ? a/d conversion mode: ordinary mode in which analog input voltages are converted into digital quantities. ? comparator mode (note 1): a mode in which analog input voltage is compared with a preset comparison voltage to find only the relative magnitude of two quantities. (useful in only single operation mode) (2) operation modes ? single mode: analog input voltage on one channel is a/d converted once or comparated (note 1) with a given quantity. ? scan mode: analog input voltages on two or more selected channels (in n channel units, n = 1?16) are sequentially a/d converted. single-shot scan mode: scan oper ation is performed for one cycle. continuous scan mode: scan operation is repeated until stopped. (3) special operation modes ? forcible single mode execution during scan mode: conversion is forcibly executed in single mode (comparator mode) during scan operation. ? scan mode start after single m ode execution: scan operation is star ted subsequently after executing conversion in single mode. ? conversion restart: a/d conversion being executed in single or scan mode is restarted. (4) sample-and-hold function the analog input voltage is sampled when starting a/d conversion, and a/d conversion is performed on the sampled voltage. this function can be enabled or disabled as necessary. (5) simultaneous sampling function optional two channels are sampled at the same time, and 2-channel continuous a/d conversion is carried out for the sampled voltage. (6) a/d disconnection detection assist function to suppress influences of the anal og input voltage leakage from an y preceding channel during scan mode operation, a function is incorporated that helps to fix the electric charge on the chopper amp capacitor to the given state (avcc or gnd) before starting a/d conve rsion. this function provides a sure and reliable means of detecting a disconnection in the wiring patterns connecting to the analog input pins. (7) inflow current bypass circuit if an overvoltage or negative voltage is applied to any analog input channel whic h is currently inactive, a current flows into or out of the analog input channel currently being a/d converted via the internal circuit, causing the conversion accuracy to degrade. to solve th is problem, the a/d conver ter incorporates a circuit that bypasses such inflow current. this circuit is always enabled.
rev.0.01 sep 21, 2004 page 30 of 32 rej03b0116-0001z 32186 group 7.1 outline of a/d converter (8) conversion speed the a/d conversion and comparat e speed can be selected from am ong 8 types: bclk mode & 2bclk mode/each slow mode & each fast mode/ each normal mode & each double speed mode. (9) interrupt request and dma transfer request generation functions an a/d conversion interrup t or dma transfer request can be generated each time a/d conversion or comparate operation in single mode is completed, as well as when a single-shot scan operation or one cycle of continuous scan operation is completed. note 1: to discriminate between the comparison performed internally by the successive approximation type a/d converter and that performed in comparator mode using the same a/d converter as a comparator, the comparison in co mparator mode is referred to in this data sheet as ?comparate.? table 7.1.1 outlines the a/d converter and figur e 7.1.1 shows block diagram of a/d converter.
rev.0.01 sep 21, 2004 page 31 of 32 rej03b0116-0001z 32186 group 7.1 outline of a/d converter note 1: the conversion accuracy stipulated here refers to that of the microcomputer al one, with influences of the power supply wiring and noise on the board not taken into account. note 2: the parenthesis ( ) indicates the value wh en the fast sample-and-hold function is effective. note 3: conversion time when f(xin) = 10 mhz (1bclk = 50 ns). table 7.1.1 outline of the a/d converter item description analog input 16 channels x 1 a/d conversion method successive approximation method resolution 10 bits (conversion result can be read out in either 8 or 10 bits) absolute accuracy (note 1) conditions: ta = 2 5 c , avcc0 = 5.12 v, vref0 = 5.12 v 2bclk mode (note 4) slow mode normal speed 2lsb (3lsb) (note 2) double speed 2lsb (3lsb) (note 2) fast mode normal speed 3lsb (3lsb) (note 2) double speed 3lsb (t.b.d) (note 2) bclk mode slow mode normal speed 2lsb (3lsb) (note 2) double speed 2lsb (3lsb) (note 2) fast mode normal speed 3lsb (3lsb) (note 2) double speed 3lsb (t.b.d) (note 2) conversion mode a/d conversi on mode and comparator mode operation mode single mode, single-s hot scan mode and continuous scan mode conversion start trigger software start started by setting the a/d conversion start bit to "1" hardware start a/d0 converter mjt (input event bus 2), mjt (input event bus 3), mjt (output event bus 3) and mjt (tin23) conversion speed (note 3) bclk peripheral clock 2bclk during single mode (when sample-and- hold disabled/ when normal sample-and- hold enabled) slow mode normal speed 598 x bclk 29.9 s double speed 346 x bclk 17.3 s fast mode normal speed 262 x bclk 13.1 s double speed 178 x bclk 8.9 s during single mode (when fast sample- and-hold enabled) slow mode normal speed 382 x bclk 19.1 s double speed 202 x bclk 10.1 s fast mode normal speed 190 x bclk 9.5 s double speed 106 x bclk 5.3 s during comparator mode slow mode normal speed 94 x bclk 4.7 s double speed 58 x bclk 2.9 s fast mode normal speed 46 x bclk 2.3 s double speed 34 x bclk 1.7 s bclk during single mode (when sample-and- hold disabled/ when normal sample-and- hold enabled) slow mode normal speed 299 x bclk 14.95 s double speed 173 x bclk 8.65 s fast mode normal speed 131 x bclk 6.55 s double speed 89 x bclk 4.45 s during single mode (when fast sample- and-hold enabled) slow mode normal speed 191 x bclk 9.55 s double speed 101 x bclk 5.05 s fast mode normal speed 95 x bclk 4.75 s double speed 53 x bclk 2.65 s during comparator mode slow mode normal speed 47 x bclk 2.35 s double speed 29 x bclk 1.45 s fast mode normal speed 23 x bclk 1.15 s double speed 17 x bclk 0.85 s sample-and-hold function sample-and-hold function can be enabled or disabled as necessary. a/d disconnection detection assist function influences of the analog input voltage l eakage from any preceding channel during scan mode operation are suppressed. interrupt request generation function generated when a/d conversion (single mo de operation, single-shot scan operation or one cycle of continuous sca n operation) or comparat e operation is completed. dma transfer request generation function generated when a/d conversion (single mo de operation, single-shot scan operation or one cycle of continuous sca n operation) or comparat e operation is completed.
rev.0.01 sep 21, 2004 page 32 of 32 rej03b0116-0001z 32186 group 7.1 outline of a/d converter figure 7.1.1 block diagram of the a/d converter ad0in0 ad0in1 ad0in2 ad0in3 ad0in4 ad0in5 ad0in6 ad0in7 selector interrupt request avss0 vref0 10-bit a/d successive approximation register (ad0sar) 10-bit a/d0 data register 0 10-bit a/d0 data register 1 a/d0 single mode register a/d0 comparate data register a/d control circuit mode selection channel selection conversion time selection flag control interrupt control 10-bit d/a converter comparator ad0in8 ad0in9 ad0n10 ad0in11 ad0in12 ad0in13 ad0in14 ad0in15 ad0cmp ad0dt0 ad0dt1 ad0dt2 ad0dt3 ad0dt4 ad0dt5 ad0dt6 ad0dt7 ad0dt8 ad0dt9 ad0dt10 ad0dt11 ad0dt12 ad0dt13 ad0dt14 ad0dt15 dma transfer request successive approximation-type a/d converter unit internal data bus a/d0 scan mode register ad0scm0,1 ad0sim0,1,2 avcc0 10-bit readout 8-bit readout shifter 10-bit a/d0 data register 2 10-bit a/d0 data register 3 10-bit a/d0 data register 4 10-bit a/d0 data register 5 10-bit a/d0 data register 6 10-bit a/d0 data register 7 10-bit a/d0 data register 8 10-bit a/d0 data register 9 10-bit a/d0 data register 10 10-bit a/d0 data register 11 10-bit a/d0 data register 12 10-bit a/d0 data register 13 10-bit a/d0 data register 14 10-bit a/d0 data register 15 input event bus 2 input event bus 3 output event bus 3 tin23s s s ad0ctrg1 ad0strg1 dma0, dma common sample & hold control circuit s comparator sample & hold control circuit
rev.0.01 sep 21, 2004 page 33 of 34 rej03b0116-0001z 32186 group 8.1 outline of serial interface 8.1 outline of serial interface the 32186 contains a total of six se rial interface channels, sio0?sio5. ch annels sio0, sio1, sio4 and sio5 can be selected between csio mode (clock-synchronous seri al interface) and uart mode (clock-asynchronous serial interface). channels sio2 and sio3 are uart mode only. ? csio mode (clock-synchronous serial interface) communication is performed synchronously with a transfer clock, using the same clock on both transmit and receive sides. the transfer data length can be selected within the range from 8 to 16 bits long. ? uart mode (clock-asynchronous serial interface) communication is performed at any transfer rate in any transfer data format. the transfer data length can be selected from 7, 8 and 9 bits. channels sio0?sio3 each have a tr ansmit dma transfer and a receive dm a transfer request. these serial interfaces, when combined with the internal dma controller (dmac), allow serial communication to be performed at high speed, as well as reduce the data communication load of the cpu. serial interface is outlined below. note 1: the maximum input frequency of an external clock during csio mode is f(bclk)/16. note 2: if f(bclk) is selected as the count source, the brg set value is subject to limitations. table 8.1.1 outline of serial interface item description number of channels csio mode/uart mode : 4 channels (sio0, sio1, sio4, sio5) uart only: 2 channels (sio2, sio3) clock during csio mode: internal clock or external clock as selected (note 1), clock polarity can be selected during uart mode: internal clock only transfer mode transmit half-duplex, receive half-duplex, transmit/receive full-duplex brg count source (when internal clock selected) f(bclk), f(bclk)/8, f(bclk )/32, f(blck)/256 (note 2) f(bclk)/2, f(bclk)/16, f(bclk)/64, f(bclk)/512 f(bclk): peripheral clock operating frequency data format csio mode: data length = selectable in the range of 8?16 bits order of transfer = selectable from lsb first or msb first uart mode: start bit = 1 bit character length = 7, 8 or 9 bits parity bit = added (odd, even) or not added stop bit = 1 or 2 bits order of transfer = selectable from lsb first or msb first baud rate csio mode: (note 1) 76 bits/sec to 2 mbits/sec (when f(bclk) = 20 mhz/internal clock selected) max 1.25 mbits/sec (when f(bclk) = 20 mhz/external clock selected) uart mode: 9.5 bits/sec to 1.25 mbits/sec (when f(bclk) = 20 mhz) error detection csio mode: overrun error only uart mode: overrun, parity and framing errors (occurrence of any of these errors is indicated by an error sum bit) fixed period clock output function when using sio0, sio1, sio4 and sio5 as uart, this function outputs a divided-by-2 brg clock from the sclk pin.
rev.0.01 sep 21, 2004 page 34 of 34 rej03b0116-0001z 32186 group 8.1 outline of serial interface figure 8.1.1 block diagram of serial interfaces sclki0/sclko0 baud rate generator (brg) internal data bus csio mode when internal clock selected csio mode uart mode when internal clock selected 1/16 1/2 rxd0 txd0 receive interrupt request transmit/ receive control circuit sio0 transmit buffer register sio0 transmit shift register receive dma transfer request transmit interrupt request transmit dma transfer request to dma3, dma4 sio0 receive shift register sio0 receive buffer register when external clock selected when uart mode selected notes: when bclk is selected, the brg set value is subject to limitations. sio2 and sio3 do not have the sclki/sclko function. sclki1/sclko1 to dma6 to the interrupt controller (icu) sio0 sio1 sio2 sio3 rxd1 txd1 transmit/ receive control circuit sio1 transmit shift register sio1 receive shift register to dma7 rxd2 txd2 transmit/ receive control circuit sio2 transmit shift register sio2 receive shift register to dma7, dma9 rxd3 txd3 transmit/ receive control circuit sio3 transmit shift register sio3 receive shift register receive interrupt request receive dma transfer request transmit interrupt request transmit dma transfer request receive interrupt request receive dma transfer request transmit interrupt request transmit dma transfer request receive interrupt request receive dma transfer request transmit interrupt request transmit dma transfer request to the interrupt controller (icu) to dma8 to dma5 to dma3, dma6 to dma4 sio4 rxd4 txd4 transmit/ receive control circuit sio4 transmit shift register sio4 receive shift register receive interrupt request transmit interrupt request sio5 rxd5 txd5 transmit/ receive control circuit sio5 transmit shift register sio5 receive shift register receive interrupt request transmit interrupt request sclki4/sclko4 sclki5/sclko5 to the interrupt controller (icu) to the interrupt controller (icu) bclk 1/2 clock divider 1/1 1/8 1/32 1/256
rev.0.01 sep 21, 2004 page 35 of 36 rej03b0116-0001z 32186 group 9.1 outli ne of the can module 9.1 outline of the can module the 32186 contains two-channel full can modules comp liant with can (controller area network) specification v2.0b active. these can modules each have 32 message sl ots and four mask registers, effective use of which helps to reduce the data processing load of the cpu. the can modules are outlined below. note 1: the maximum allowable error of oscillation depends on the system configuration (e.g ., bus length, clock error, can bus transceiver, sampling position and bit configuration). note 2: it depends on a clock to be supplied to the protocol engine block in the can module. table 9.1.1 outline of the can module item description protocol can specification v2.0b active number of message slots total 32 slots (30 global slots, two local slots) polarity 0: dominant 1: recessive acceptance filter (function to receive only a range of ids specified by receive id filter) global mask: 2 local mask: 2 baud rate 1 time quantum (tq) = (brp + 1) / (cpuclk/4 or cpuclk/2) (note 2) (brp: baud rate prescaler set value) baud rate = 1 . . . max 1 mbps (note 1) tq period x number of tq?s for one bit brp: 1 ? 255 (0: inhibited) number of tq?s for one bit = synchronization segment + propagation segment + phase segment 1 + phase segment 2 synchronization segment: 1tq propagation segment: 1 ? 8tq phase segment 1: 1 ? 8tq phase segment 2: 1 ? 8tq (ipt = 1) remote frame automatic response function the slot that received a remote frame responds by automatically sending a data frame. timestamp function this function is implemented us ing a 16-bit counter. the count period is derived from the can bus bit period by dividing it by 1, 2, 3 or 4. basiccan mode double buffer function is materialized using two local slots. transmit abort function transmit requests can be canceled. loopback function the can module receives th e data transmitted by the module itself. return bus off function error active mode is forcibly entered into after clearing the error counter. single shot function transmission is not retried even wh en it failed due to arbitr ation-lost or a transmit error. dma transfer function dma transfer request is generated when transmi ssion failed or transmit/receive operation finished. self-diagnostic function communication module is di agnosed by communicating internally in the can module.
rev.0.01 sep 21, 2004 page 36 of 36 rej03b0116-0001z 32186 group 9.1 outli ne of the can module figure 9.1.1 block diagram of the can modules acceptance filter self- diagnosis control baud rate prescaler cpuclk/4 message slot 32 transmit/receive completed, error or single shot dma0, 6 dma2, 7 can0 internal data bus interrupt crx0 dam request can protocol controller acceptance filter self- diagnosis control baud rate prescaler cpuclk/4 message slot 32 transmit/receive completed, error or single shot can1 interrupt ctx1 crx1 can protocol controller dam request dma5, 8 dma7, 9 ctx0
rev.0.01 sep 21, 2004 page 37 of 37 rej03b0116-0001z 32186 group 10.1 outline of the direct ram interface (dri) 10.1 outline of the dir ect ram interface (dri) the direct ram interface (dri) is a pa rallel interface used to take in paralle l data into the internal ram as it is input to the microcomputer synchronously with the cloc k. since a dedicated bus provided separately from the m32r-fpu is used to write data from the dri to the inte rnal ram, data can be taken in without having to stop operation of the m32r-fpu. furthermore, a selective data capture function is supported that makes use of the internal event counter of the dri. note : ? when f(bclk) = 80mhz. figure 10.1.1 block diagram of the direct ram interface (dri) table 10.1.1 outline of the direct ram interface (dri) item function transfer method clock synchronous parallel input ram access area entire 64 kbytes area of the internal ram received data width selectable from 32, 16 and 8 bits maximum transfer rate 20 mbytes/sec minimum data capture cycle 200ns (when the special mode not selected, with input data bus width 32 bits), 175ns (when the special mode not selected, with input data bus width 16/8 bits), 100ns (when the special mode selected) data capture bus width 32/16/8 bits (when the special mode not selected), 16/8 bits (when the special mode selected) event counter 16 bits x 5 counters (dec0 ? dec4) bank switch function two banks in ram specifiable as data storage destination data capture edge selectable from rising or falling edge or both edges capture timing adjust function timing from data capture edge detection to data sampling can be set selective data capture function data can be capt ured selectively using an internal event counter din0 din1 din2 din3 din4 din0 din1 din2 din3 din4 tio8(f/f19) top8(f/f8) tou0_7(f/f28) tou1_7(f/f36) din5 event detection circuit (din0 ? din5) dd0 ? dd31 dd input pin select circuit (dd input enable/ disable control) dri capture control circuit dri transfer control circuit dri event counters (dec0 ? dec4) dri event detection interrupt request (din0 ? din5 event detection) dri counter interrupt request (dec0 ? dec4 underflow) dri transfer interrupt request (dri address counter 0 transfer completed dri address counter1 transfer completed overrun error capture enable error dri transfer counter underflow) dri address bus (to the internal ram) dri data bus (to the internal ram)
rev.0.01 sep 21, 2004 page 38 of 38 rej03b0116-0001z 32186 group 11.1 outline of the real-time debugger (rtd) 11.1 outline of the real-time debugger (rtd) the real-time debugger (rtd) is a seri al interface through which to read or write to any location in the entire area of the internal ram by using comm ands from outside the microcomputer. because data transfers between the rtd and internal ram are performed via a dedicated internal bus independently of the m32r-fpu, rtd operation can be controlled withou t the need to stop the m32r-fpu. figure 11.1.1 block diagram of the real-time debugger (rtd) table 11.1.1 outline of the real-time debugger (rtd) item description transfer method clock-synch ronous serial interface generation of transfer clock generated by external host ram access area entire area of the internal ram (controlled by a14 ? a29) transmit/receive data length 32 bits (fixed) bit transfer sequence lsb first maximum transfer rate 2 mbits/second input/output pins 4 pins (rtdtxd, rtdrxd, rtdack, rtdclk) number of commands following five functions ? monitor continuously ? output real-time ram content ? forcibly rewrite ram content (with verify) ? recover from runaway condition ? request rtd interrupt control circuit commands data data address address data rtd control circuit entire area of internal ram m32r-fpu core address data bus switching circuit rtdclk rtdclk rtdack rtdtxd rtdrxd
rev.0.01 sep 21, 2004 page 39 of 40 rej03b0116-0001z 32186 group 12.1 outline of the non-break debug (nbd) 12.1 outline of the non-break debug (nbd) non-break debug (nbd) has the ram monitor and event output functions. a dedicated dma is incorporated in nbd, so that accesses to the internal ram, etc. are accomplished using this dma. (1) ram monitor function this function is provided for reading and writing to an d from all resources connected to the internal/external buses mapped in the address space. it allows the ram da ta, etc. to be referenced and altered. furthermore, accesses to the address space used exclusively for nbd (i .e., nbd space) are accomplis hed using this function. (2) event output function upon detecting access to a preset addr ess, this function outputs a low-leve l signal from the nbdevnt# pin. a specific address and read/write access can be specified as the even t occurrence condition. table 12.1.1 outline of the non-break debug (nbd) item content transfer method clock-synchronou s parallel interface (4 bits) transfer clock generation generated by external host access area all areas in the address map and nbd space access size 8, 16 or 32 bits (for nbd space, fixed to 8 bits) maximum transfer rate 12.5mhz input/output pins 7 pins (nbdd3 ? nbdd0, nbdclk, nbdsync#, nbdevnt#) functions ? ram monitor function ? event output function number of events set 1 event
rev.0.01 sep 21, 2004 page 40 of 40 rej03b0116-0001z 32186 group 12.1 outline of the non-break debug (nbd) figure 12.1.1 block diagram of the non-break debug (nbd) dma for nbd event detection block nbd register internal 32-bit bus internal flash memory nbd internal 16-bit bus m32r-fpu core internal bus interface nbdd3(p77/rxdclk/crx1) nbdclk(jtclk) nbdsync#(jtdi) nbdevnt#(jtdo) internal ram external bus sfr area nbdd0(p74/rtdtxd/txd3) nbdd1(p75/rtdrxd/rxd3) nbdd2(p76/rtdack/ctx1)
rev.0.01 sep 21, 2004 page 41 of 41 rej03b0116-0001z 32186 group 13.1 virtual flash emulation function 13.1 virtual flash emulation function the microcomputer has the function to map 8-kbyte memory blocks of the internal ram (max. 8 blocks) into areas (l banks) of the internal flash memory that are divide d in 8-kbyte units. this functions is referred to as the virtual flash emulation function. this function allows the data located in 8-kbyte blocks of the internal ram to be changed with the contents of internal flash memory at the addresse s specified by the virtual flash l bank register. that way, the relevant ram data can read out by reading the content of internal flash memory. for applications that require modifying the contents of internal flash memory (e.g., data table) during operation, this function enables dynamic data modification by modifying the relevant ram data. the ram blocks allocated for virtual fl ash emulation can be accessed for read and write the same way as in usual ram. this function, when used in combination with the microcomputer?s internal real-time debugger (rtd), allows the data table, etc. created in the internal flash memory to be referenced or rewr itten from the outside, thereby facilitating data table tuning from an external device. note: ? before programming/erasing the internal flash memory, always be sure to exit this virtual flash emulation mode. figure 13.1.1 internal ram bank configuration of the 32186 h'0080 4000 h'0080 5fff h'0080 6000 h'0080 7fff h'0080 8000 h'0080 a000 h'0080 bfff h'0080 c000 h'0080 dfff h'0080 e000 h'0080 9fff h'0081 0000 h'0081 1fff h'0081 2000 h'0081 3fff h'0080 ffff ram bank l block 0 (felbank0) 8 kbytes ram bank l block 1 (felbank1) 8 kbytes ram bank l block 2 (felbank2) 8 kbytes ram bank l block 3 (felbank3) 8 kbytes ram bank l block 4 (felbank4) 8 kbytes ram bank l block 5 (felbank5) 8 kbytes ram bank l block 6 (felbank6) 8 kbytes ram bank l block 7 (felbank7) 8 kbytes
rev.0.01 sep 21, 2004 page 42 of 43 rej03b0116-0001z 32186 group 14.1 outline of the wait controller 14.1 outline of the wait controller the wait controller controls the number of wait states inserted in bus cycl es when accessing an external extension area. the wait controller is outlined in the table below. during external extension and processor modes, four chip select signals (cs0# to cs3#) are output, each corresponding to one of the four external ex tension areas referred to as cs0 through cs3. figure 14.1.1 cs0 ? cs3 area address map table 14.1.1 outline of the wait controller item description target space control is applied to the following address spaces depending on operation mode: single-chip mode: no target space (settings of the wait controller have no effect) external extension mode: cs0 area (7 mbytes), cs1 area (8 mbytes), cs2 area (8 mbytes), cs3 area (8 mbytes) processor mode: cs0 area (8 mb ytes), cs1 area (8 mbytes), cs2 area (8 mbytes), cs3 area (8 mbytes) number of wait states 0 ? 15 wait states set by software + any number of wait states set from the wait# pin that can be inserted h'0000 0000 h'0010 0000 h'000f ffff h'0100 0000 h'007f ffff h'0200 0000 h'017f ffff h'0300 0000 h'027f ffff h'037f ffff internal rom area cs0 area (7mb) cs1 area (8mb) cs2 area (8mb) cs3 area (8mb) cs0 area (8mb) cs1 area (8mb) cs2 area (8mb) cs3 area (8mb) non-cs0 area (internal rom access area) h'0080 0000 h'00ff ffff h'0180 0000 h'01ff ffff h'0280 0000 h'02ff ffff extended external area extended external area ghost of cs1 area (8mb) ghost of cs1 area (8mb) ghost of cs2 area (8mb) ghost of cs2 area (8mb) h'03ff ffff h'0380 0000 ghost of cs3 area (8mb) ghost of cs3 area (8mb)
rev.0.01 sep 21, 2004 page 43 of 43 rej03b0116-0001z 32186 group 14.1 outline of the wait controller when accessing the external exte nsion area, the wait controller controls th e number of wait st ates inserted in bus cycles based on the number of wait states set by software and the input signal entered from the wait# pin. the number of wait states that can be controlled in software is 0 to 15. when the input signal on the wait# pin is sampled low in the last cycle of internal wait state, the wait state is extended as long as the wait# input signal is held low. then when the wait# input sign al is released back high, the wait state is terminated and the next new bus cycle is entered into. note 1: a ghost (8 mbytes) of the cs1 area will appear in the h'0180 0000 to h'01ff ffff area. note 2: a ghost (8 mbytes) of the cs2 area will appear in the h'0280 0000 to h'02ff ffff area. note 3: a ghost (8 mbytes) of the cs3 area will appear in the h'0380 0000 to h'03ff ffff area. table 14.1.2 number of wait states th at can be set by the wait controller external extension area address number of wait states inserted cs0 area h?0010 0000 to h?007f ffff zero to 15 wait states set by software (external extension mode) + any number of wait states entered from the wait# pin h?0000 0000 to h?007f ffff (however, software settings have priority.) (processor mode) cs1 area (note 1) h?0100 0000 to h?017f ffff zero to 15 wait states set by software (external extension and processor modes) + any number of wait states entered from the wait# pin (however, software settings have priority.) cs2 area (note 2) h?0200 0000 to h?027f ffff zero to 15 wait states set by software (external extension and processor modes) + any number of wait states entered from the wait# pin (however, software settings have priority.) cs3 area (note 3) h?0300 0000 to h?037f ffff zero to 15 wait states set by software (external extension and processor modes) + any number of wait states entered from the wait# pin (however, software settings have priority.)
rev.0.01 sep 21, 2004 page 44 of 45 rej03b0116-0001z 32186 group 15.1 instruction set 15.1 instruction set cpu instruction set the m32r employs a risc architecture, supporting a total of 100 discrete instructions. (1) load/store instructions perform data transfer between memory and registers ld load ldb load byte ldub load unsigned byte ldh load halfword lduh load unsigned halfword lock load locked st store stb store byte sth store halfword unlock store unlocked (2) transfer instructions perform register to register transfer or register to imme- diate transfer ld24 load 24-bit immediate ldi load immediate mv move register mvfc move from control register mvtc move to control register seth set high-order 16-bit (3) branch instructions used to change the program flow bc branch on c-bit beq branch on equal beqz branch on equal zero bgez branch on greater than or equal zero bgtz branch on greater than zero bl branch and link blez branch on less than or equal zero bltz branch on less than zero bnc branch on not c-bit bne branch on not equal bnez branch on not equal zero bra branch jl jump and link jmp jump nop no operation (4) arithmetic/logic instructions perform comparison, arithmetic /logic operation, multipli- cation/division, or shift between registers ? comparison cmp compare cmpi compare immediate cmpu compare unsigned cmpui compare unsigned immediate ? logical operation and and and3 and 3-operand not logical not or or or3 or 3-operand xor exclusive or xor3 exclusive or 3-operand ? arithmetic operation add add add3 add 3-operand addi add immediate addv add (with overflow checking) addv3 add 3-operand addx add with carry neg negate sub subtract subv subtract (with overflow checking) subx subtract with borrow ? multiplication/division div divide divu divide unsigned mul multiply rem remainder remu remainder unsigned ? shift sll shift left logical sll3 shift left logical 3-operand slli shift left logical immediate sra shift right arithmetic sra3 shift right arithmetic 3-operand srai shift right arithmetic immediate srl shift right logical srl3 shift right logical 3-operand srli shift right logical immediate (5) instructions fo r the dsp function perform 32-bit x 16-bit or 16 -bit x 16-bit multiplication or sum-of-products calculation these instructions also perform rounding of the accumu- lator data or transfer between accumulator and general- purpose register. machi multiply-accumulate high-order halfwords maclo multiply-accumulate low-order halfwords macwhi multiply-accumulate word and high-order halfword macwlo multiply-accumulate word and low-order halfword mulhi multiply high-order halfwords mullo multiply low-order halfwords mulwhi multiply word and high-order halfword mulwlo multiply word and low-order halfword mvfachi move from accumulator high-order word mvfaclo move from accumulator low-order word mvfacmi move from accumulator middle-order word mvtachi move to accumulator high-order word mvtaclo move to accumulator low-order word rac round accumulator rach round accumulator halfword (6) eit related instructions start trap or return from eit processing rte return from eit trap trap
rev.0.01 sep 21, 2004 page 45 of 45 rej03b0116-0001z 32186 group 15.1 instruction set figure 15.1.1 instructions for the dsp function h l h l h l 63 h l h l x x hl x x 32bit 0 0 63 15 16 31 32 47 48 acc rsrc1 rsrc2 mulhi instruction mullo instruction 15 16 31 0151631 0 rsrc1 rsrc2 15 16 31 0151631 0 rsrc1 rsrc2 31 0151631 0 32bit rsrc1 rsrc2 31 0151631 0 063 acc 063 acc 063 acc 063 acc 063 acc mulwhi instruction mulwlo instruction 063 063 acc 0 0 63 63 acc rac instruction sign data sign data rach instruction 031 0313263 acc mvtachi instruction mvtaclo instruction rsrc 0 31 mvfachi instruction mvfacmi instruction mvfaclo instruction rdest 0 0 acc macwhi instruction macwlo instruction machi instruction maclo instruction x x + + x x + + (7) instructions for the fpu function the microcomputer supports fully ieee754 compliant, single-precision floating-point arithmetic. fadd floating-point add fsub floating-point subtract fmul floating-point multiply fdiv floating-point divide fmadd floating-point multiply and add fmsub floating-point multiply and subtract itof integer to float utof unsigned to float ftoi float to integer ftos float to short fcmp floating-point compare fcmpe floating-point compare with exception if unordered (8) extended instructions sth store halfword (@r+ addressing added) bset bit set bclr bit clear btst bit test setpsw set psw clrpsw clear psw
rev.0.01 sep 21, 2004 page 46 of 46 rej03b0116-0001z 32186 group 16.1 package dimensions 16.1 package dimensions lqfp144-p-2020-0.50 weight(g) 1.23 jedec code eiaj package code lead material cu alloy 144p6q-a plastic 144pin 20 ? 20mm body lqfp 0.125 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 0.95 m d 20.4 m e 20.4 8 0 0.1 1.0 0.65 0.5 0.35 22.2 22.0 21.8 22.2 22.0 21.8 0.5 20.1 20.0 19.9 20.1 20.0 19.9 0.175 0.125 0.105 0.27 0.22 0.17 1.4 0.05 1.7 e a h d d h e e 1 36 37 72 73 108 109 144 f e lp 0.45 0.6 0.25 0.75 0.08 x a3 m d l 2 b 2 m e e recommended mount pad y b x m a 1 a 2 l 1 l detail f lp a3 c recommended
a -47 revision history 32186 group data sheet rev. date description page summary 1.00 dec 01, 2004 ? first edition issued
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is al ways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating i n the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents in formation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or e rrors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technolo gy corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under cir cumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materia ls. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. unit2607 ruijing building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ? 2004. renesas technology corp., all rights reserved. printed in japan. colophon .2.0

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